Steps to avoid racing condition in JK Flip flop:
- If the Clock On or High time is less than the propagation delay of the flip flop then racing can be avoided. This is done by using edge triggering rather than level triggering.
- If the flip flop is made to toggle over one clock period then racing can be avoided.
Keeping this in consideration, why is it called JK flip flop?
Actually, the choice of the letters "JK" in the JK flip flop do have significance. The JK flip flop was named after Jack Kilby, the Texas Instruments engineer that invented the integrated circuit in 1958. The modified RS circuit that eliminated race conditions was named JK in his honor.
What is a JK flip flop?
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”.
What is set and reset in flip flops?
Set-Reset Flip-Flop Operations. The set/reset type flip-flop is triggered to a high state at Q by the "set" signal and holds that value until reset to low by a signal at the Reset input. This can be implemented as a NAND gate latch or a NOR gate latch and as a clocked version.